1. Technical Field
The present invention relates to electronic circuits in general, and in particular to flip-flop circuits. Still more particularly, the present invention relates to a single-event upset immune flip-flop circuit.
2. Description of the Related Art
Flip-flop circuits are widely found in digital circuits because flip-flop circuits are one of the most commonly used elements to implement sequential circuits. Sequential circuits are circuits in which a primary output relies not only on the current value of an input, but also the previous input value. A flip-flop circuit can be used to generate a steady state output signal having either a logical high potential (one) or a logical low (zero) potential.
Referring now to the drawings and, in particular, to FIG. 1, there is depicted a schematic diagram of a flip-flop circuit according to the prior art. As shown, a flip-flop circuit 10 includes a p-channel transistor 15 and three n-channel transistors 16-18 connected in series between a high potential 11 and a ground potential 12, a p-channel transistor 19 and three n-channel transistors 20-22 connected in series between high potential 10 and ground potential 12, three inverters 13, p-channel transistors 23-24, and a latch 14. Inverters 13 are coupled in series between a clock signal input 25 and the gate of transistor 18. Clock signal input 25 is also connected to the gates of transistors 15, 16 and 20. The complement of clock signal input 25 is connected to the gates of transistors 18, 22 and 24. A data input 26 is connected to the gates of transistors 17 and 23. A node 27, which is located between transistors 15 and 16, is connected to the gates of transistors 19 and 21. Transistors 23 and 24 are connected between high potential 10 and node 27. Latch 14 is connected to node 28 located between transistors 19 and 20 to provide an output 29.
During operation, when clock signal CK at clock signal input 25 is at a logical low state, node 27 is precharged to a logical high state, and transistors 18, 22 are turned on, while transistors 16, 20 are turned off. At this point, node 28 holds its value from a previous clock cycle. On the rising edge of clock signal CK at clock signal input 25, transistor 15 is turned off and transistors 16, 20 are turned on. Transistors 18, 22 remain turned on for the delay period of inverters 13. Data D at data input 26 is sampled during this period. If data D at data input 26 is at a logical low state, node 27 remains at a logical high state, and node 28 either remains at a logical low state or is pulled to a logical low state through transistors 20-22. If data D at data input 26 is at a logical high, node 27 is discharged to a logical low state through transistors 16-18, and node 28 remains at a logical high state or is pulled up to a logical high state through transistor 19.
One problem with prior art flip-flop circuits, such as flip-flop circuit 10, is that they are very susceptible to single-event upsets (SEUs) or single-event transients (SETs). For example, if there is an SEU occurred on the data input path, then runt pulses may occur on the data path and subsequently erroneous data occur at the output. Consequently, it is desirable to provide an SEU immune flip-flop circuit.
In accordance with a preferred embodiment of the present invention, a single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.